It has been approved by both theory and empirical studies that when a stress is applied to the channel of a transistor, the carrier mobility of the transistor will be enhanced or reduced; however, it is also known that electrons and holes may have different responses to the same type of stress. For example, application of compressive stress in a longitudinal direction of flow of electrical current is advantageous to hole mobility, but is not advantageous to electron mobility, and application of tensile stress in a longitudinal direction is advantageous to electron mobility, but is not advantageous to hole mobility. With continuous reduction in the device feature size, stress channel engineering for the purpose of enhancing the channel carrier mobility plays a more and more important role. Multiple uniaxial process induced stresses are integrated to a device process. In terms of the optimal introducing direction of the uniaxial process induced stress, as for an NMOS device, introduction of tensile stress in a direction along the channel, that is, direction X as well as introduction of compressive stress in a direction perpendicular to the channel direction, that is, direction Z are most effective for enhancing the mobility of electrons in the channel, as shown in FIG. 1; on the other hand, as for a PMOS device, introduction of compressive stress in a direction X is most effective for enhancing the mobility of holes in the channel. A lot of methods have been developed based on this theory. One of the methods is to produce “global stress”, that is, the stress being applied to the overall transistor device area produced from the substrate. The global stress is produced by using the structures such as SiGe stress relaxed buffer layer, SiC stress relaxed buffer layer or SiGe structure on an insulator. Another method is to produce “local stress”, that is, the stress being merely applied from the local structure to the local area adjacent to the channel. The local stress is produced by using the structures such as shallow trench isolation structure that produces a stress, (dual) stress liner, SiGe (e-SiGe) structure embedded into source/drain (S/D) area of a PMOS, Σ-shaped SiGe (e-SiGe) structure embedded into source/drain (S/D) area of a PMOS, and SiC (e-SiC) structure embedded into the source/drain (S/D) area of an NMOS. However, among the above methods for changing the stress in a channel, some require a complicated process, and some may introduce defects to the channel. On the other hand, with continuous reduction in the device feature size, the induced stress effect brought forward by the above method is continuously weakened.
In view of the above reason, there still exists a need for providing a semiconductor structure which is capable of realizing adjustable channel stress for both NMOS and PMOS devices.